EasyTrig
EasyTrig reference library

Calculators & generators

Find a tool by name, topic, or the quantity you need to calculate.

13 tools

ToolWhat it doesSubject
Phasor addition on a complex plane with solid, dashed and dotted vectorsPhasor calculator

Add, subtract, multiply, and divide in rectangular or polar form.

Circuits & signals
Three phasors rendered as monochrome sinusoidal waveformsPhasor & sinusoid plotter

Compare time-domain waveforms with explicit amplitude and phase conventions.

Circuits & signals
Complex vectors plotted against real and imaginary axesComplex number plotter

Plot vectors on the complex plane and inspect magnitude and argument.

Circuits & signals
Discrete-time signal displayed as individual samples on a stem plotDiscrete-time signal plotter

Evaluate sequences, inspect samples, and fit manually entered points.

Circuits & signals
Fixed-point conversion of -1.375 to the 16-bit hexadecimal word EA00Fixed-point converter

Encode and decode signed or unsigned binary fixed-point values.

FPGA engineering
FPGA clock-enable calculation showing a divisor of 100000 and a 17-bit counterClock divider & enable

Find an integer division ratio, frequency error, and counter width.

FPGA engineering
DDS calculation showing tuning word 42949673 for a 32-bit phase accumulatorDDS tuning word

Calculate a phase increment, achieved frequency, and tuning resolution.

FPGA engineering
AMD Xilinx block RAM estimate showing four RAMB36 primitives for 4096 by 32 bitsFPGA memory sizing

Estimate block RAM requirements from width, depth, and primitive mode.

FPGA engineering
FPGA timing calculation showing 3.35 ns setup slack and 0.4 ns hold slackSetup & hold timing

Check a single-cycle path with clock skew and uncertainty.

FPGA engineering
UART baud-rate calculation showing divisor 54 and approximately 0.469 percent errorUART baud-rate divider

Choose a sampling divider and quantify baud-rate error.

FPGA engineering
SystemVerilog testbench clock results and generated simulation codeSystemVerilog clock generator

Generate simulation clocks with frequency, duty cycle, and time precision.

HDL & documents
Generated VHDL entity with clock, reset and eight-bit input and output portsVHDL entity & testbench

Build a typed entity interface and a matching simulation scaffold.

HDL & documents
Markdown source beside rendered engineering notes with LaTeX equationsMarkdown to PDF

Preview Markdown and mathematics, then print a paginated document.

HDL & documents