UART baud-rate divider calculator
Choose an integer baud divider for a custom FPGA UART and calculate the resulting serial timing and payload rate.
Calculator
Divider and frame equations
For a UART that divides a clock by integer N and oversamples by M, baud = fclock / (M × N). The calculator compares the adjacent integer divisors to minimize absolute baud error. A counter that counts from zero uses terminal count N − 1.
Frame length is one start bit + data bits + an optional parity bit + stop bits. Continuous frames per second equals actual baud divided by frame length. Useful payload throughput multiplies this frame rate by the number of data bits.
Worked example
For a 100 MHz clock, 115,200 baud, and 16× oversampling, the selected divisor is 54. Actual baud is about 115,740.741 bit/s, an error of +0.4694%. An 8N1 frame contains ten bits.
Applying the result
The calculation covers integer-divider UARTs. Fractional dividers and phase accumulators can achieve different errors. Check the specific UART core’s divisor-register convention and supported frame formats, especially 1.5 stop bits and nine-bit data.
Successful reception depends on the combined transmitter/receiver frequency mismatch, sampling architecture, start-edge uncertainty, frame length, and channel quality. There is no universal safe error threshold. Compare both ends’ oscillator tolerances and the target core’s documentation.
Related tools
- FPGA clock-enable divider — Generate a synchronous counter for a periodic sampling enable.
- SystemVerilog clock generator — Create reference clocks for a serial-interface simulation.
- Setup and hold timing budget — Check the synchronous register paths in a custom UART implementation.
