SystemVerilog Clock Generator

Module name Enable signal Outputs

Timeunit/precision 1ns/1ps 1us/1ns 100ps/1ps 1ms/1us Preset None 3 outputs: 100MHz, 50MHz, 10MHz 2 outputs: 1MHz 30%, 10kHz 60% Reset

Actions Generate SystemVerilog Copy Download .sv

Each output can use frequency or period with its own duty cycle. Enable gates all clocks.