DDS tuning-word calculator

Calculate the nearest tuning word for a binary phase accumulator, with the actual output frequency and frequency resolution. Use it when designing a numerically controlled oscillator in FPGA logic.

Calculator

Phase-accumulator equations

For a binary accumulator updated once per sample, K = round_even(f_out × 2^N / f_sample). The realized frequency is K × f_sample / 2^N, and the frequency step is f_sample / 2^N. The tuning word is rounded using exact decimal ratios and integer arithmetic. Displayed frequencies use floating-point arithmetic.

Example

For a 100 MHz sample clock, a 32-bit accumulator, and a requested 1 MHz output, K is 42,949,673 (0x028F5C29). The realized frequency is approximately 1,000,000.000931 Hz.

Frequency range and implementation

This tool covers nonnegative output frequencies from DC through half the sample rate. At exactly Nyquist, the sampled waveform depends on phase and can degenerate to zero for a sine lookup. Frequencies above half the sample rate alias into the baseband.

Phase width determines the tuning resolution. Amplitude width, phase truncation, dithering, DAC response, and output filtering separately affect spectral quality. For time-multiplexed channels, enter the sample update rate for one channel. AMD DDS Compiler rasterized mode uses a programmable modulus and requires a different calculation.

Fixed-point converter — Choose the representation used for quantized waveform amplitudes.
FPGA memory sizing — Estimate block RAM for a waveform lookup table.
Discrete-time signal plotter — Inspect sample sequences and sinusoidal expressions.

DDS calculation showing tuning word 42949673 for a 32-bit phase accumulator — For a 100 MHz sample clock and a requested 1 MHz output, a 32-bit accumulator uses tuning word 42,949,673. The result table reports the achieved frequency and quantization error.

DDS tuning-word calculator

Calculator

Phase-accumulator equations

Example

Frequency range and implementation

Related tools

References