AMD Xilinx block RAM sizing
Compare block RAM aspect ratios for a logical memory. The estimate includes width lanes and depth banks so that narrow, deep, or unusually wide memories are accounted for.
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How the estimate works
For every supported primitive shape, blocks = ⌈logical width / primitive width⌉ × ⌈logical depth / primitive depth⌉. The result chooses the smallest count when every primitive uses the same shape. The bit-capacity lower bound is ⌈total bits / primitive capacity⌉.
The RAMB18 configurations are 16,384 × 1, 8,192 × 2, 4,096 × 4, 2,048 × 9, and 1,024 × 18, with 512 × 36 in simple-dual-port mode. RAMB36 doubles the depth for the shared widths, adds 1,024 × 36, and supports 512 × 72 in simple-dual-port mode.
Worked example
A 4,096 × 32-bit memory maps to four RAMB36 primitives in 4,096 × 9 mode, or four in 1,024 × 36 mode. The best same-shape count is four and physical bit utilization is 88.89%.
Scope of the estimate
These shapes apply to 7-series RAMB18E1/RAMB36E1 and UltraScale RAMB18E2/RAMB36E2. The calculation assumes equal read/write widths, available parity storage as data, and ECC disabled. Simple dual port means one read port and one write port.
Mixed-shape packing, asymmetric ports, byte-write enables, ECC, cascade constraints, extra read ports, and synthesis choices can change usage. Confirm the final result in Vivado synthesis and implementation reports. A one-word memory needs zero address bits mathematically; an HDL interface may still require a minimum one-bit address signal.
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